The 2026-07-11 dev-repo record stands, but the publish half it
describes (add_all index staging, mixed-reset reconcile) was replaced
by the splice + soft-reset replay, and the reconcile path is now
hardware-verified. Point to the kaizen and the tradeoff curve for the
real-repo numbers (24.1 s cold :gp).
The design record for Typoena — the decisions, specs, and bench write-ups
behind the writing appliance. Start with the ADRs for the
load-bearing choices, or the v0.1 specs for what the
first release actually does.
4ead64bada