Translates user-facing requirements (the WHATs) into engineering
functions (the HOWs) and components, with a House-of-Quality matrix,
roof tradeoffs, function→component mapping (anchored to ADRs), and a
critical performance budget keyed to upcoming spikes. Cross-references
adr.md throughout.
Prior text said "~40 KB of stack space"; the v0.1 technical design's
task table sums to 76 KB (usb 8 + wifi 8 + ui 16 + render 12 + git 32).
Also widens the std::thread stack-cost note from a flat 8 KB to 8–32 KB
to match the per-task budget. No design change — 76 KB still fits
comfortably in the ESP32-S3's 512 KB internal SRAM.
Strip-aspect 5.79" panel (792×272) replaces the page-shaped 7.5" choice.
Reflows the v0.1 screen layout, framebuffer memory budget, and spike 2
acceptance to validate the SSD1683-class controller path or fall back to
a ~300 LoC custom embedded-hal driver.
