feat(firmware): drive GDEY0579T93 EPD via dual-SSD1683 driver
Add a thin dual-SSD1683 driver (src/epd.rs, ported from GxEPD2's GxEPD2_579_GDEY0579T93) for the 792x272 e-paper panel: reset/init, RAM addressing, the split-and-mirror full-frame blit across the master/slave seam at x=396, and full-refresh waveform. Frame implements embedded-graphics' DrawTarget. Replace the Spike 1 blink harness in main.rs with the Spike 2 test: SPI at 4 MHz over SCK 12 / DIN 11 / CS 7 / DC 6 / RST 5 / BUSY 4, alternating normal/inverted frames with a seam-straddling circle, "Typoena", and the build tag. Verified on hardware 2026-07-04.
This commit is contained in:
Julien Calixte
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firmware/src/epd.rs
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321
firmware/src/epd.rs
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//! Thin SSD1683 driver for the GDEY0579T93 (792×272) e-paper panel.
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//!
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//! This panel is a *dual-controller* device: 792×272 exceeds one SSD1683's
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//! 400×300 limit, so it is driven as a **master** (command offset `0x00`) +
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//! **slave** (`0x80`) pair, with the framebuffer split between them. The
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//! command sequences and RAM-window math are ported faithfully from GxEPD2's
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//! `GxEPD2_579_GDEY0579T93` (Jean-Marc Zingg), itself based on the Good
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//! Display factory demo. See `docs/v0.1-mvp-technical.md` (Spike 2) and
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//! ADR-003.
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//!
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//! **Spike 2a scope:** hardware reset, init, uniform full-screen fill, full
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//! refresh — enough to prove wiring + SPI + both controllers + refresh.
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//! Text (an `embedded-graphics` `DrawTarget` + the per-quadrant blit from
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//! GxEPD2's `_writeFromImage`) is Spike 2b.
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use embedded_graphics::pixelcolor::BinaryColor;
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use embedded_graphics::prelude::*;
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use esp_idf_svc::hal::delay::FreeRtos;
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use esp_idf_svc::hal::gpio::{Input, Output, PinDriver};
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use esp_idf_svc::hal::spi::{SpiBusDriver, SpiDriver};
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use esp_idf_svc::sys::EspError;
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pub const WIDTH: u16 = 792;
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pub const HEIGHT: u16 = 272;
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/// Each controller drives one half. SSD1683 X is byte-addressed; 396 px
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/// rounds up to 50 bytes (400 px) of RAM width, full panel height (272 rows).
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const CTRL_BYTES_W: usize = 50;
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const CTRL_BYTES: usize = CTRL_BYTES_W * HEIGHT as usize; // 50 * 272 = 13600
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/// Full-frame 1-bit framebuffer: 792 px = 99 bytes per row, MSB-first,
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/// 1 = white, 0 = black (SSD16xx convention).
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pub const FB_BYTES_W: usize = (WIDTH / 8) as usize; // 99
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pub const FB_BYTES: usize = FB_BYTES_W * HEIGHT as usize; // 26928
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/// In-memory 792×272 1-bit frame, drawable via `embedded-graphics`.
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/// `BinaryColor::On` = black ink, `Off` = white paper.
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pub struct Frame {
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buf: Vec<u8>,
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}
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impl Frame {
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pub fn new_white() -> Self {
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Self { buf: vec![0xFF; FB_BYTES] }
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}
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pub fn new_black() -> Self {
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Self { buf: vec![0x00; FB_BYTES] }
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}
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pub fn bytes(&self) -> &[u8] {
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&self.buf
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}
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}
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impl OriginDimensions for Frame {
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fn size(&self) -> Size {
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Size::new(WIDTH as u32, HEIGHT as u32)
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}
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}
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impl DrawTarget for Frame {
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type Color = BinaryColor;
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type Error = core::convert::Infallible;
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fn draw_iter<I>(&mut self, pixels: I) -> Result<(), Self::Error>
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where
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I: IntoIterator<Item = Pixel<Self::Color>>,
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{
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for Pixel(p, color) in pixels {
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if (0..WIDTH as i32).contains(&p.x) && (0..HEIGHT as i32).contains(&p.y) {
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let idx = p.y as usize * FB_BYTES_W + p.x as usize / 8;
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let bit = 0x80u8 >> (p.x % 8);
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match color {
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BinaryColor::On => self.buf[idx] &= !bit, // black ink
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BinaryColor::Off => self.buf[idx] |= bit, // white paper
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}
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}
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}
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Ok(())
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}
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}
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/// Max bytes per SPI transfer; matches the DMA size configured in `main`.
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const SPI_CHUNK: usize = 4096;
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pub struct Epd<'d> {
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spi: SpiBusDriver<'d, SpiDriver<'d>>,
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dc: PinDriver<'d, Output>,
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rst: PinDriver<'d, Output>,
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cs: PinDriver<'d, Output>,
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busy: PinDriver<'d, Input>,
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}
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impl<'d> Epd<'d> {
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pub fn new(
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spi: SpiBusDriver<'d, SpiDriver<'d>>,
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dc: PinDriver<'d, Output>,
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rst: PinDriver<'d, Output>,
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cs: PinDriver<'d, Output>,
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busy: PinDriver<'d, Input>,
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) -> Self {
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Self { spi, dc, rst, cs, busy }
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}
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// ---- low-level SPI framing (DC low = command, DC high = data) ----
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fn cmd(&mut self, c: u8) -> Result<(), EspError> {
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self.dc.set_low()?;
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self.cs.set_low()?;
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self.spi.write(&[c])?;
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self.cs.set_high()?;
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Ok(())
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}
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fn data(&mut self, bytes: &[u8]) -> Result<(), EspError> {
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self.dc.set_high()?;
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self.cs.set_low()?;
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for chunk in bytes.chunks(SPI_CHUNK) {
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self.spi.write(chunk)?;
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}
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self.cs.set_high()?;
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Ok(())
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}
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/// BUSY is active-HIGH on this panel (GxEPD2 constructs with `HIGH`).
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fn wait_while_busy(&mut self, timeout_ms: u32) -> Result<(), EspError> {
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let mut waited = 0;
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while self.busy.is_high() {
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FreeRtos::delay_ms(1);
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waited += 1;
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if waited >= timeout_ms {
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log::warn!("EPD BUSY still high after {timeout_ms} ms — continuing");
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break;
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}
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}
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Ok(())
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}
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// ---- panel bring-up ----
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/// Hardware reset (RST is active-low). ~20 ms pulses per GxEPD2 default.
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pub fn reset(&mut self) -> Result<(), EspError> {
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self.rst.set_high()?;
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FreeRtos::delay_ms(20);
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self.rst.set_low()?;
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FreeRtos::delay_ms(20);
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self.rst.set_high()?;
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FreeRtos::delay_ms(20);
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self.wait_while_busy(100)?;
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Ok(())
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}
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/// Port of GxEPD2 `_InitDisplay` (B/W mode). The `0x20` master
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/// activations load the temperature value and LUT.
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pub fn init(&mut self) -> Result<(), EspError> {
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self.cmd(0x12)?; // SWRESET
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FreeRtos::delay_ms(10);
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self.wait_while_busy(100)?;
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self.cmd(0x18)?; // temperature sensor control
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self.data(&[0x80])?; // internal sensor
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self.cmd(0x22)?; // display update control 2
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self.data(&[0xB1])?; // enable clock, load temp, load LUT (B/W), disable clock
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self.cmd(0x20)?; // master activation
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FreeRtos::delay_ms(10);
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self.wait_while_busy(100)?;
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self.cmd(0x1A)?; // write to temperature register
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self.data(&[0x64, 0x00])?;
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self.cmd(0x22)?;
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self.data(&[0x91])?; // load temp, load LUT (B/W), disable clock
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self.cmd(0x20)?;
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FreeRtos::delay_ms(10);
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self.wait_while_busy(100)?;
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Ok(())
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}
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/// Port of GxEPD2 `_setPartialRamArea`. `target` is `0x00` (master) or
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/// `0x80` (slave); `mode` selects X/Y increment/decrement (0x00–0x03).
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fn set_ram_area(
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&mut self,
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x: u16,
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y: u16,
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w: u16,
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h: u16,
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mode: u8,
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target: u8,
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) -> Result<(), EspError> {
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self.cmd(0x11 | target)?; // data entry mode
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self.data(&[mode])?;
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let xl = (x / 8) as u8;
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let xh = ((x + w - 1) / 8) as u8;
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let ys = [(y % 256) as u8, (y / 256) as u8];
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let ye = [((y + h - 1) % 256) as u8, ((y + h - 1) / 256) as u8];
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match mode {
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0x03 => {
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// X increment, Y increment
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self.cmd(0x44 | target)?;
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self.data(&[xl, xh])?;
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self.cmd(0x45 | target)?;
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self.data(&[ys[0], ys[1], ye[0], ye[1]])?;
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self.cmd(0x4E | target)?;
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self.data(&[xl])?;
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self.cmd(0x4F | target)?;
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self.data(&[ys[0], ys[1]])?;
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}
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0x02 => {
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// X decrement, Y increment
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self.cmd(0x44 | target)?;
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self.data(&[xh, xl])?;
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self.cmd(0x45 | target)?;
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self.data(&[ys[0], ys[1], ye[0], ye[1]])?;
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self.cmd(0x4E | target)?;
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self.data(&[xh])?;
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self.cmd(0x4F | target)?;
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self.data(&[ys[0], ys[1]])?;
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}
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0x01 => {
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// X increment, Y decrement
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self.cmd(0x44 | target)?;
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self.data(&[xl, xh])?;
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self.cmd(0x45 | target)?;
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self.data(&[ye[0], ye[1], ys[0], ys[1]])?;
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self.cmd(0x4E | target)?;
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self.data(&[xl])?;
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self.cmd(0x4F | target)?;
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self.data(&[ye[0], ye[1]])?;
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}
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_ => {
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// 0x00: X decrement, Y decrement
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self.cmd(0x44 | target)?;
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self.data(&[xh, xl])?;
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self.cmd(0x45 | target)?;
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self.data(&[ye[0], ye[1], ys[0], ys[1]])?;
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self.cmd(0x4E | target)?;
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self.data(&[xh])?;
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self.cmd(0x4F | target)?;
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self.data(&[ye[0], ye[1]])?;
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}
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}
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FreeRtos::delay_ms(2);
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Ok(())
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}
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/// Fill one RAM bank (`0x24` current or `0x26` previous) on both
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/// controllers with a constant byte. One clean full-coverage window per
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/// controller (slave = left half `0x80`, master = right half `0x00`) —
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/// simpler and more complete than GxEPD2's overlapping-window fill, which
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/// only matters for a constant value anyway.
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fn write_buffer(&mut self, command: u8, value: u8) -> Result<(), EspError> {
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let buf = vec![value; CTRL_BYTES];
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for target in [0x80u8, 0x00u8] {
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self.set_ram_area(0, 0, 400, HEIGHT, 0x03, target)?;
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self.cmd(command | target)?;
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self.data(&buf)?;
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}
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Ok(())
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}
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/// Port of GxEPD2 `refresh(false)` → `_Update_Full` (fast full update).
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fn update_full(&mut self) -> Result<(), EspError> {
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self.set_ram_area(0, 0, WIDTH / 2, HEIGHT, 0x03, 0x80)?; // slave
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self.set_ram_area(0, 0, WIDTH / 2, HEIGHT, 0x03, 0x00)?; // master
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self.cmd(0x21)?; // display update control 1
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self.data(&[0x40, 0x10])?; // bypass RED as 0, cascade
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self.cmd(0x1A)?; // temperature register (fast full update)
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self.data(&[0x64, 0x00])?;
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self.cmd(0x22)?;
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self.data(&[0xD7])?; // fast full update
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self.cmd(0x20)?; // master activation
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self.wait_while_busy(2500)?; // full_refresh_time ≈ 2200 ms
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Ok(())
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}
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/// Fill the whole panel with one value and full-refresh.
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/// `0xFF` = white, `0x00` = black. Port of GxEPD2 `clearScreen`.
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pub fn clear_screen(&mut self, value: u8) -> Result<(), EspError> {
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self.write_buffer(0x26, value)?; // previous
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self.write_buffer(0x24, value)?; // current
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self.update_full()?;
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Ok(())
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}
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/// Blit a full 792×272 framebuffer into one RAM bank on both
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/// controllers. Port of the full-frame case of GxEPD2 `_writeFromImage`:
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/// slave gets panel bytes 0..=49 of each row in X-increment mode; the
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/// master's sources are wired mirrored, so it gets bytes 49..=98 in
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/// bitmap order while the address counter walks RAM 49..=0 (mode 0x02).
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/// The seam byte 49 (px 392..399) lands on both; the 4 columns past each
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/// controller's 396 sources aren't wired.
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fn write_frame_bank(&mut self, command: u8, fb: &[u8]) -> Result<(), EspError> {
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let mut buf = Vec::with_capacity(CTRL_BYTES);
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for y in 0..HEIGHT as usize {
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let row = &fb[y * FB_BYTES_W..(y + 1) * FB_BYTES_W];
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buf.extend_from_slice(&row[..CTRL_BYTES_W]);
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}
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self.set_ram_area(0, 0, WIDTH / 2, HEIGHT, 0x03, 0x80)?; // slave
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self.cmd(command | 0x80)?;
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self.data(&buf)?;
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buf.clear();
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for y in 0..HEIGHT as usize {
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let row = &fb[y * FB_BYTES_W..(y + 1) * FB_BYTES_W];
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buf.extend_from_slice(&row[FB_BYTES_W - CTRL_BYTES_W..]);
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}
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self.set_ram_area(0, 0, WIDTH / 2, HEIGHT, 0x02, 0x00)?; // master
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self.cmd(command)?;
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self.data(&buf)?;
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Ok(())
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}
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/// Show a full 792×272 framebuffer (`FB_BYTES` long) with a full
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/// refresh. Writes both RAM banks so the next differential update has a
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/// consistent "previous" image.
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pub fn display_frame(&mut self, fb: &[u8]) -> Result<(), EspError> {
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assert_eq!(fb.len(), FB_BYTES, "framebuffer must be 99 x 272 bytes");
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self.write_frame_bank(0x26, fb)?; // previous
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self.write_frame_bank(0x24, fb)?; // current
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self.update_full()?;
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Ok(())
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}
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}
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